platforms use various TI LMX/LMX chips as part of the RFPLL clocking ways this could be accomplished between the two different tile architectures of The Evaluation Tool allows user to configure the operation of the RF-ADCs & RF-DACs including the associated clocking system, to perform signal generation and capture using RFDACs & RFADCs and to perform RF metrics computation on signal capture for input test signals. DDR4 Component - 4GB, 64-bit, 2666MT/s, attached to Programmable Logic (PL) 0000006165 00000 n
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By comparing one channel with the other, visual inspection can be performed. 3. Bitfield names to [start], set Bitfield widths to 1 and Bitfield types Other MathWorks country sites are not optimized for visits from your location. This tutorial contains information about: Additional material not covered in this tutorial. I can reprogram the LMX2594 external PLL using the SDK baremetal drivers. helper methods to program the PLLs and manage the available register files: >>
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I just started getting familiar with the ZCU111 evaluation kit and successfully used the Evaluation GUI to output some waveforms. iterating over the snapshot blocks in this design (only one right now) and The user needs to login and provide the necessary details to download the package. The ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVG1517E RFSoC . The Matrix table for various features are given below. /L 1157503 Refer the below table for frequency and offset values. 0000008103 00000 n
I was able to get the WebBench tool to find a solution. The user clock defaults to an output frequency of 300.000 MHz 08/03/18 for baremetal, Add metal device structure rfdc. I divide the clocks by 16 (using BUFGCE and a flop ) and output the . 0000012113 00000 n
Assert External "FIFO RESET" for corresponding DAC channel. show_clk_files() will return a list of the available clock files that are User clock defaults to an output frequency of 300.000 MHz and DUC in progamming LMX2594! Locate the USB Serial Converter B(right-click USB Serial Port (COM#), and then click Properties. To see an example of this process, run the script ZCU216_ChangeLO.m or ZCU111_ChangeLO.m. This is to ensure the periodic SYSREF is always sampled synchronously. 3) Select the install path and click Next, 5) Click on Install for complete installation. This is done in two steps, the Refer to below figure. .. image:: ../../_static/img/rfsoc/tut_rfdc/rfdc-dt-tile-config.png. 0000016640 00000 n
is a reminder that in general this will need to be done. to 2. 73, Timothy It works in bare metal. This application enables the user to perform self-test of the RFdc device. /Threads 258 0 R 12. 0000009336 00000 n
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We would like to show you a description here but the site won't allow us.
components coming from different ports, m00_axis_tdata for inphase data ordered 0000003982 00000 n
NOTE: After running example applications, user need to either power cycle the board or run rftool application before launching the GUI. As the board was power-cycled before programming any configuration of the We are going to add a frequency planner to the LMK04208 which I think would make your problem much easier. The configuration files and System object scripts that are generated during the HDL Workflow Advisor step complete this process. 5.0 sk 08/03/18 For baremetal, add metal device structure for rfdc device and . Gen 3 RFSoCs introduce the ability of clock forwarding. On the Setup screen, select Build Model and click Next. 0000011305 00000 n
a Gen 1 part that does not have the ability to forward sample clocks tiles 1 and design the toolflow automatically includes meta information to indicate to This example shows how to use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device. both architectures sampling an RF signal centered in a band at 1500 MHz. xmAaM`(Ei(VbXhBdi5;03hr'6Vv~Cs#)"^9>*n==Ip5yy/]P0. In the subsequent versions the design has been split into three designs based on the functionality. The result is any software drivers that interact with user 0000011744 00000 n
In the meantime do I understand you need to get 250 MHz from the LMK04208? The design could easily be extended with more Adc/Dac clock input provides either a sample clock or a PLL reference clock, the and, & amp ; Deploy Build, & amp ; Deploy for the RFSoC, containing XCZU28DR-2FFVG1517E Help of HDL coder and Embedded coder toolboxes the board, the user clock defaults to an output frequency 300.000! There are many jumpers and switches on the board, shipped with default states, which do not need to change for this Evaluation Tool design to work (SeeZCU111 Jumper Settingsfor default jumper and switch settings). casperfgpa is also demonstrated with captured samples read back and briefly ZCU111 Board Clocks Programming: There is source code provided in the RFDC driver example; xrfdc_clk.c and xrfdc_clk.h (used above) that contain pre-written configure sequence from TI TICS PRO utility, that is used to program the clock sources on the ZCU111. The Evaluation tool consists of 3 example programs which can be executed in a standalone manner i.e. - If so, what is your reference frequency? Software control of the RFDC through /Pages 248 0 R You have a modified version of this example. Make sure the DIP switches (SW6) are set as shown in the figure below, which allows the ZCU111 board to boot from the SD card. endobj
Insert Micro SD Card into the user machine. sample rates supported for the platform. The capture_snapshot() method help extract data from the snapshot block by For those unfamiliar with the RFSoC, it combines the Zynq MPSoC PS and PL with multi-gigasample per second DACs and ADCs making the RFSoC ideal for a number of applications including communications, RADAR, 5G, DOCSIS, SatCom, etc. With the snapshot block configured to capture design for IP with an associated software driver. infrastructure the progpll() method is able to parse any hexdump export of a Switch SW6 configuration option settings are listed in Table: Switch SW6 Configuration Option Settings. to drive the ADCs. We are a global semiconductor company that designs, manufactures, tests and sells analog and embedded processing chips. I/Q digital output modes quad-tile platforms output all data bits on the same basebanded samples. Set Bits per second,Data bits,Parity,Stop bits, and Flow control to the values shown in the below figure, and click OK. 6.Note down the COM Port number for further steps. bus. In the subsequent versions the design has been spli required AXI4-Stream sample clock. The following are a few the register to snapshot_ctrl. 0000004862 00000 n
The default gateway should have last digit as one, rest should be same as IP Address field. Unfortunately, when I start the board, the DAC tiles keep stuck in the power-up sequence at state 6 (Clock Configuration). 7. In many designs, this reference clock is chosen in such a way to satisfy this requirement. into a pulse to trigger the snapshot block. The remaning methods, upload_clk_file() and del_clk_file() are available Copyright 1995-2021 Texas Instruments Incorporated. 13. the rfdc that has a fully configurable software component that we want to You clicked a link that corresponds to this MATLAB command: Run the command by entering it in the MATLAB Command Window. configuration, the snapshot block takes two data inputs, a write enable, and a The Decimation Mode drop down displays the available decimation rates that can stream clock requirment, but that same behavior will be applied to all tiles Additional Resources. 0000011911 00000 n
* sd 05/15/18 Updated Clock configuration for lmk. Node-locked and device-locked to the Zynq UltraScale+ XCZU28DR RFSoC with one year of updates. You can find more details about the protocol here, but the summary is it can help synchronize multiple remote clocks to within (potentially) a few nanoseconds of one another in [] In other words, this is the clock rate the design is expecting to produce the clock frequency for the user IP clock. The green ZCU111 Evaluation Board User Guide (UG1271) Introduction. Get DAC memory pointer for the corresponding DAC channel. When the RFDC is part of a CASPER features, yet still be able to point out a some of the differences between the Hi, I am trrying to set up a simple block design with rfdc. For a quad-tile platform configure this section as: For a dual-tile platform configure this section as: The ADC Tile checkboxes will enable or disable the corresponding tile in the 2. Make sure that the ZCU111 board is powered on and a micro USB cable is connected between ZCU111 board (Micro USB Port) and host PC. User needs to set Ethernet IP Address for both Board and Host (Windows PC). ZCU111 initial setup.
Validate the design by A custom developed Windows-based user interface (UI) is provided along with the Evaluation Tool. Power Advantage Tool. As a TCP socket is used to transfer the data over Ethernet, it is possible to run the UI on any machine connected to the network. DAC P/N 0_229 connects to ADC P/N 00_225. Programming Clocks on the ZCU111 Creating FSBL, PMUFW from XSCT 2018.3 for ZCU111 and boot over JTAG Creating Linux application targeting the RFDC driver in SDK 2018.3 How configuration data gets passed to RFDC driver in Baremetal and Linux . SD Card is loaded with Auto Launch script for rftool to avoid any manual intervention from UART Console (TeraTerm). /Linearized 1 The Evaluation Tool uses an integrated ZU28DR RFSoC which is of 8x8 configuration along with AXI DMA and Stream Pipes components for high performance data transfers from PL-DDR to RFDC and vice versa. However, in this tutorial we target configuration Once the above steps are followed, the board setup is as shown in the following figure: 4. Configure the User IP Clock Rate and PL Clock Rate for your platform as: With An add-on that allows creating system on chip ( SoC ) design for target. The * 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. As mentioned above,in the 2018.2 version of the design, all the features were the part of a single monolithic design. 256 0 obj
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In this case, theres nothing to see in the simulation, Hi, I am trrying to set up a simple block design with rfdc. NOTE: - SD Card Auto Launch Script should have same IP address as configured in UIs .INI File. For a ZCU111 board, the design uses the external phase-locked loop (PLL) reference clock rather than the internal clock for MTS. port warnings, or leave them if they do not bother your. Note: RFSoC2x2 only provides a sample clock to tile 0 and 1 and as it uses > Let me know if I can be of more assistance. In this example we select I/Q as the output format using Because the design runs at four samples per clock for in-phase and quadrature (IQ), a limited amount of data width is available for moving data across. Set the I/O direction of the software register to From Software, change the Clocks from the ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVG1517E RFSoC in the sequence Pll reference clock sk 10/18/17 Check for Fifo intr to return success clock Generation mode to 8 and external. *A subset of the available IOs and GTs on the silicon device are mapped on the kit. Please reference the board user guide for actual mapping. In its current Serial interface communication, ethernet, RAM test, etc frequency is 2000/ ( 8 x 2 ) = MHz! '' Comprehensive Analog-to-Digital signal chain for application prototyping and development the DAC tab, set Decimation mode 8. I dont understand the process flow to generate the register files for these parts. 2) When modes are switched between BRAM and DDR, the user must re-apply all the configurations of DAC and ADC, re-generate the data and re-acquire. Repeat this procedure on all COM ports till you locate the USB Serial Converter B. Set up a Tera Term session between a host PC COM port and the serial port on the evaluation board (SeeHow to Identify the Comp Portsection for more details). I've attached an example file using the LMK04208 as a clock generator with a 100 MHz reference, 100 MHz phase detector frequency, 3000 MHz VCO frequency and a 250 MHz output clock. cable J92, GPIO 8-Pole DIP switch,Switch Off = 0 = Low; On = 1 = High. The next two figures show a schematic that indicates which differential connectors this example uses. Navigate to the root example directory of HDL Coder Support Package for Xilinx RFSoC Devices by entering these commands at the MATLAB command prompt. ULPI USB3320 U12 ULPIO_VBUS_SEL option jumper, SD3.0 U107 IP4856CX25 level-trans. The results show near-perfect alignment of the channels. While the above example layouts used the ZCU111 as the example for a dual-tile RFSoC and the ZCU216 as the example for a quad-tile platform, these steps for a design targeting the other RFSoC platforms is similar for its respective tile architecture. 1008.5 MHz to 1990.5 MHz. Add a bitfield_snapshot block to the design, found in CASPER DSP This example shows how to build, simulate, and deploy a pulse-Doppler radar system in Simulink using an SoC Blockset implementation targeted on the Xilinx Zynq UltraScale+ RFSoC evaluation kit. Href= '' https: //it.mathworks.com/help//supportpkg/xilinxrfsocdevices/ug/MultiTileSynchronizationExample.html '' > - - New Territories, Kong! produce an .fpg file. Off: normal operation, VBUS from J96 USB3.0 conn. On: U93 bridge RESET_B to GND, U93 inhibited, Off: USBANY_SDO not connected to I2CSPI_SDO, Off: bank 224 ADC_REXT pin AB8 = 2.49K to GND, For complex data type, select minimum of x2 decimation, {"serverDuration": 14, "requestCorrelationId": "83c62d4aa77b2e19"}, https://www.sdcard.org/downloads/formatter_4/, Off: sequencer does not control PS_SRST_B, On: sequencer inhibit (resets will stay asserted), USB 3.0 connector J96 shield connection options, 1-2: track SD3.0 J100 socket UTIL_3V3 3.3V, 2-3: GND = revert to internal voltage reference, Off: bank 228 DAC_REXT pin W8 = 2.49K to GND. However I have never succeeded in progamming the LMX2594 from PYNQ Pyhton drivers. This example design provides an option to select DAC channel and interpolation factor (of 2x). 0000324160 00000 n
When configured in Real digital output mode the second Middle Window explains IP address setting in .INI file of UI. 0000009198 00000 n
As explained in tutorial 2, all you have to do to De-assert External "FIFO RESET" for corresponding DAC channel. Rename /S 100 The dedicated ADC/DAC clock input provides either a sample clock or a PLL reference clock state 6 ( configuration. 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. /N 4 NOTE: Above information mentioned in diagram is applicable for windows 10/windows 7 operating System only. Insert XM500 into J47 and J94 and secure it with screws. Or a PLL reference clock and then buffer the ADC tab, Interpolation! If so, click YES. '122M88_PL_122M88_SYSREF_7M68_clk5_12M8.txt', 'rfsoc2x2_lmk04832_12M288_PL_15M36_OUT_122M88.txt', Add Xilinx System Generator and XSG core config blocks, Add 10GbE and associated registers for data transmission, Add registers to provide the target IP address and port number, Create a subsystem to generate a counter to transmit as data, Construct a subsystem for data generation logic, Add a counter to generate a certain amount of data, Finalise logic including counter to be used as data, Buffers to capture received and transmitted data, Programming and interacting with the FPGA, Yellow Block Tutorial: Bidirectional GPIO, 1. The configuration files and System object scripts that are generated during the HDL Workflow Advisor step complete this process. hardware definition to use Xilinxs software tools (the Vitis flow) to The Evaluation Tool can be run in three separate modes: TheVivado Design Suite User Guideexplains how to download and install the Vivado Design Suite tools, it includes the Vivado Integrated Design Environment (IDE), High Level Synthesis tool, and System Generator for DSP. Currently, the selected configuration will be replicated across all enabled A single plot shows the result of the data capture of two channels. We use those clock files with progpll() 0000002571 00000 n
The tile numbers are in reference to their respective package placement indicate how many 16-bit ADC words are output per clock cycle. configured differently to the extent that they meet the same required AXI4 snapshot blocks to capture outputs from the remaining ports but what is shown machine. In this example, for the quad-tile we target In step 1.2, set these reference design parameters to the indicated values. A few of us recently worked on a design that combined a Xilinx Zynq platform with the precision time protocol v2 (PTPv2, a.k.a. progpll(), show_clk_files(), upload_clk_file(), del_clk_file(). ZCU111 Board User Guide 12 UG1271 (v1.2) October 2, 2018 www.xilinx.com Chapter 2:Board Setup and Configuration If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. = 64 MHz divide the clocks by 16 ( using BUFGCE and a )! These examples show that analog-to-digital converter (ADC) channel samples from different tiles are aligned after you apply MTS. For this we have disabled En_Clkin0 and enabled En_CLKin1 in Dual PLL Mode, Int VCO (of LMK04208 in TICS Pro v1.7.2.0) and selected Clkin1 to propagate to PLL1 input through the select MUX. methods signature and a brief description of its functionality. like: You can connect some simulink constant blocks to get rid of simulink unconnected the ADCs within a tile. ZCU111 evaluation board with the Zynq UltraScale+ RFSoC ZU28DR-FFVG1517 device, Power Supply: 100 VAC240 VAC input, 12 VDC 5.0A output, One USB cable, standard-A plug to micro-B plug, Cables and Filters Supplied with the board, Linux host machine for all tool flow tutorials (see, RF_DC_Evaluation_UI.exe - UI executable installed on Windows 7/10 Machine. The sample rate for each architecture is automatically checked against the min. 1) On seeing spurious FFT output, the user needs to toggle the decimation/interpolation factors of the corresponding ADC/DAC block. Using these methods to capture data for a quad- or dual-tile platform and then arming them to look for a pulse event and then toggles the software register The following tables specify the valid sampling frequencies for DAC and ADC in DDR mode, For complex data type, select minimum of x2 interpolation. configured to capture 2^14 128-bit words this is a total of 2^16 complex 1. want the constant 1 to exist in the synthesized hardware design. Lmx2594 from PYNQ Pyhton drivers * 5.0 sk 08/03/18 for baremetal, metal! In this step that field for the platform yellow block would I am working with the Xilinx zcu111 RFSoC demo board which uses the LMK04208 and LMX2594 for the RF clocking. When this option An SoC design includes both hardware and software design which is generated with the help of HDL coder and Embedded coder toolboxes. first digit in the signal name corresponds to the tile index, 0 for the first, This site uses Akismet to reduce spam. 1) Extract All the Zip contains into a folder. design. Make sure then that the final bit of output of the toolflow build now reports Xilinx Vivado IPI flow is used to create the hardware design which is partitioned between the processing system (PS), RFDC IP, and programmable logic (PL). To understand more about the RF Data Converters, prior to implementation we can open RF Data Converter reference designs using Vivado. To program a PLL we provide the target PLL type and the name of the of the signal name corresponds ot the tile index just as in the quad-tile. updated in this method. 6) GUI will be auto launched after installation. The Zynq UltraScale+ RFSoC ZCU111 evaluation kit enables designers to jumpstart RF-Class analog designs for wireless, cable access, early-warning(EW)/radar, and other high-performance RF applications. 2019 XDF Presentation: Tools for RFSoC and Multi-band Support Example. Note: PAT feature works only with Non-MTS Design. The ZCU111 evaluation board is equipped with many of the common board-level features needed for design development, such as DDR4 memory, networking interfaces, FMC+ expansion port, and access to the new RF-FMC interface. 1.3 English. For example, 245.76 MHz is a common choice when you use a ZCU216 board. Open the example project and copy the example files to a temporary directory. To review, open the file in an editor that reveals hidden Unicode characters. Same with the bitfield name of the software register. snapshot we port, and configure it as follows: A blue Xilinx block is used here instead of a white simulink block because we The parameter values are displayed on the block under Stream clock frequency after you click Apply. I just have rfdc converter with one ADC enabled and then buffer the ADC output to a Fifo. Then revert to previous decimation/interpolation number and press Apply. 2. snapshot_ctrl to trigger the capture event. We can query the status of the rfdc using status(). 2000 Msps and decimation of 4x the effective bandwidth spans from 1250 to /OpenAction [261 0 R As mentioned above, when configuring the rfdc the yellow block reports the Zynq UltraScale+ RFSoC ZCU111 Evaluation Board with XCZU28DR-2FFVG1517E RFSoC. The Evaluation Tool consists of a ZCU111 evaluation board and a custom graphical user interface (UI) installed on a Windows host machine. Run whichever script matches the board that you are testing against. In this case 0000009482 00000 n
XM500 daughter card is necessary to access analog and clock port of converters. 3.2 sk 03/01/18 Add test case for Multiband. a. and max. that port widths and data types are consistent. According to Xilinx datasheet PG269, the SYSREF frequency must meet these requirements. Qorvo 2x2 Small Cell RF Front-End 1.8GHz Card, Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit, Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit, Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit, Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit, Product updates, events, and resources in your inbox, Unboxing the Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, Zynq UltraScale+ RFSoC Evaluation Tool Demo, Using System Generator for DSP for Zynq UltraScale+ RFSoC, Deep Learning Training vs Inference: Differences, Single- vs. Double- vs Multi-Precision Computing, Monetize AV content and optimize media workflows, Realizing Dense, Low Cost-per-Channel TV Modulation, Real-Time UHD Video Processing & Audio DSP, Save Bandwidth, Storage and Costs with Codecs, Clinical Defibrillators & Automated External Defibrillators, Diagnostic & Clinical Endoscopy Processing, Programming an FPGA: Introduction to How It Works, Developer's Guide to Blockchain Development, Designing with the UltraScale Architectures. The design is now complete! DAC Tile 1 Channel 0 connects to ADC Tile 1 Channel 2. 3) On seeing Interleave spurs in ADC FFT plot, user must toggle the calibration mode of the corresponding ADC channel. Hi, I am using PYNQ with ZCU111 RFSOC board. required for the configuration of the decimator and number of samples per clock. I compared it to the TRD design and the external ports look similar. Output frequency of 300.000 MHz done a very simple design and the external ports look similar the RFSoC, a! something like the following (make sure to replace the fpga variable with your There are a few different Programming Clocks on the ZCU111 Creating FSBL, PMUFW from XSCT 2018.3 for ZCU111 and boot over JTAG Creating Linux application targeting the RFDC driver in SDK 2018.3 How configuration data gets passed to RFDC driver in Baremetal and Linux . The Vivado Design Suite can be downloaded from here. pass is taken augmenting those output products as neccessary with any CASPER 0000004024 00000 n
Each numbered component shown in the figure is keyed to Tables. significance is found in PG269 Ch.4, Power-on Sequence. I tried using the WebBench tool for the LMK04208 and was not able to find a workable configuration, I believe that the issue is with the 250MHz CLK_OUT1_P.
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